1. Field of the Invention
This invention relates to a semiconductor memory device, especially relates to a column redundancy system for replacing a defective column with a redundant column.
2. Description of Related Art
In a semiconductor memory with a large capacitance, it is usually equipped with a redundancy system for relieving a defective chip. In detail, this type memory has in the chip a defective address storage circuit and an address comparison circuit for comparing an external address with the defective address stored in the defective address circuit. When an external address is input, the address comparison circuit compares it with the defective addresses, and outputs a replace signal when address matching is detected, thereby replacing a defective address cell with a redundant cell array.
A NAND-type flash memory, which is known as one of electrically rewritable and non-volatile memories (EEPROMs), has also such a redundancy system (see, for example, Unexamined Japanese Patent Application Publication No. 2002-100192).
The defective address storage circuit is usually formed of a fuse circuit or a ROM circuit. There has already been provided a method of storing defective address data in a memory cell array together with various initial setup data without the fuse circuit or ROM circuit (see, for example, Unexamined Japanese Patent Application Publication No. 2001-176290).
Especially in the NAND-type flash memory, as the capacitance becomes greater, the column numbers become more. In case the column numbers are increased more, it is required of the memory chip to be increased in the redundant column numbers for securing a constant relief efficiency. Further, in case the redundant column numbers are increased more, the chip occupying area of the defective address circuit and address comparison circuit will be increased more.
In the conventional redundant system, even if the defective addresses are stored in the memory cell array, it is necessary for disposing the address comparison circuit for detecting whether an input address is matched with a defective address or not. Further, in the conventional redundant system, there is a problem that it takes a long access time because it is required of externally supplied address data to be transferred through the address comparison circuit.